1. Field of the Invention
The present invention relates to insulated gate field effect transistor devices and more particularly to a method of fabricating such devices with lateral stepped reductions in drain and source dopant concentration.
2. Description of the Prior Art
Insulated gate field effect transistors ("IGFETs") take their name from the structure of the device in the vicinity of the transistor gate. The gate electrode, herein typically doped polysilicon, is separated from doped semiconductor material by a silicon dioxide insulating layer. Imposition of an electric potential on the gate electrode results in the development of an electric field which attracts charge carriers toward the electrode. The charge carriers are prevented from reaching the electrode by the insulating layer, but provide a conductive path between the transistor source and drain in the semiconductor material adjacent the insulating layer.
The development of field effect transistors in integrated circuits has resulted in and points to still further miniaturization. However, in maintaining compatability with existing systems, the scale of power supply voltages used in conjunction with such devices has not been decreased. Accordingly, electric field strength levels have increased with each decrease in size of the devices as a result of geometric shaping and reduced distances. The effects of strong electric fields within IGFET devices include reduction of carrier mobility, and, particularly in N channel devices, impact ionization and hot electron injection into the silicon dioxide insulating layer adjacent the field effect transistor gate. Energized electrons which surmount the silicon/silicon dioxide energy barrier become trapped within the gate insulating layer and can affect the threshold voltage of the device as well as producing other undesirable effects, such as reduced conductivity.
One solution to this problem has been the lightly doped drain-source (LDD) N channel insulated gate field effect transistor.
The lightly doped drain-source structure introduces narrow, lightly doped N type regions between the channel and the more heavily doped N type source and drain regions. The effect of the interposed, more lightly doped N type conductivity regions is to spread out the electric field, particularly at the drain pinch-off region, to reduce maximum field magnitude.
An example of such a device is disclosed in U.S. Pat. No. 4,599,118 by Han et al. The Han et al. patent describes implanting at least a first reduced concentration region between the highly concentrated drains and sources and the gate region of the opposite conductivity type.
However, processes such as that disclosed in Han et al. are complex and involve steps not useful for the fabrication of other devices in an integrated circuit.